Workshops Archive

Second International Workshop on RISC-V for HPC

Workshop: Second International Workshop on RISC-V for HPC

Authors: Nick Brown (Edinburgh Parallel Computing Centre (EPCC), University of Edinburgh); John Davis (Barcelona Supercomputing Center (BSC)); John Leidel (Tactical Computing Laboratories, Texas Advanced Computing Center); Michael Wong (Codeplay); and Andy Gothard (Siemens)

Abstract: RISC-V is an open standard Instruction Set Architecture (ISA) which enables the open development of CPUs and a shared common software ecosystem. There are already approximately 10 billion RISC-V cores, which is expected to accelerate rapidly. Nonetheless, for all the successes that RISC-V has faced, it is yet to become popular in HPC. Recent advances however, such as the vectorisation standard and data center RISC-V-based CPUs, mean that this technology is becoming a more realistic proposition for our workloads.

This workshop aims to connect those currently involved in RISC-V with the wider HPC community. We look to bring together RISC-V experts with scientific software developers, vendors, and supercomputing center operators to explore the advantages, challenges, and opportunities that RISC-V can bring to HPC. Furthermore, we aim to further expand the RISC-V HPC SIG, enabling interested attendees to participate in one of the most exciting open-source technological activities of our time.

Website: https://riscv.epcc.ed.ac.uk/community/sc23-workshop/

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