The International Conference for High Performance Computing, Networking, Storage, and Analysis
The International Conference for High Performance Computing, Networking, Storage, and Analysis
Workshop: LLVM-HPC2023: The Ninth Workshop on the LLVM Compiler Infrastructure in HPC
Authors: Muhammad Usman (Barcelona Supercomputing Center), Sergio Iserte (Barcelona Supercomputing Center (BSC)), and Roger Ferrer and Antonio J. Peña (Barcelona Supercomputing Center)
Abstract: DPUs as network co-processors are an emerging trend in our community. These have been generally used as domain-specific accelerators transparent to application developers; In the HPC field, DPUs have been used as MPI accelerators, but also to offload some tasks from the general-purpose processor. However, the latter required application developers to deploy MPI ranks in the DPUs, as if they were remote (weak) compute nodes, hence considerably hindering programmability. The wide adoption of OpenMP as the threading model in the HPC arena, along with that of GPU accelerators, is making OpenMP offloading to GPUs a wide trend for HPC applications. In this paper we introduce, for the first time in the literature, OpenMP offloading support for network co-processor DPUs. We present our design in LLVM to support OpenMP standard offloading semantics and discuss the programming productivity advantages with respect to the existing MPI-based programming model.
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