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Accelerator Integration in a Tile-Based SoC: Lessons Learned with a Hardware Floating Point Compression Engine

Workshop: RSDHA: Redefining Scalability for Diversely Heterogeneous Architectures

Authors: Xueyang Liu (Georgia Institute of Technology); Patricia Gonzalez-Guerrero (Lawrence Berkeley National Laboratory (LBNL)); Ivy (Bo) Peng (KTH Royal Institute of Technology, Sweden); Ronald Minnich (Samsung Corporation); and Maya Gokhale (Lawrence Livermore National Laboratory)

Abstract: Heterogeneous Intellectual Property (IP) hardware acceleration engines have emerged as a viable path forward to improving performance in the waning of Moore’s Law and Dennard scaling. In this study, we design, prototype, and evaluate the HPC-specialized ZHW floating point compression accelerator as a resource on a System on Chip (SoC). Our full hardware/software implementation and evaluation reveal inefficiencies at the system level that significantly throttle the potential speedup of the ZHW accelerator. By optimizing data movement between CPU, memory, and accelerator, 6.9X is possible compared to a RISC-V64 core, and 2.9X over a Mac M1 ARM core.

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