Installed in May 1995, it came in at number three on the June 1995 TOP500 list with a Rpeak rating of 154 Gflops. Standing next to the system are Ken Kliewer and Arthur Bland.
Image Credit: Curtis Boles, ORNL (1996)
Intel Paragon MP3 Node Board
Dimensions: 10.375 x 14.5 in (26.4 x 36.8 cm)
Date: ca. 1994
Manufacturer: Intel
Artifact loan courtesy of The CPU Shack, Klamath Falls, OR
This Intel Paragon MP3 node board has three Intel i860XP-50 processor chips with each one supplying up to 75 Mflops of double-precision computing power. In addition, the board has forty DRAM memory chips offering 32 Mbytes of local ECC memory for these CPUs. When installed in a fully configured system, such as the Paragon XPS/150 at Oak Ridge National Laboratory with 1,024 MP3 node boards (see photo above), it helped to deliver over 150 Gflops of processing power.
Announced in 1991, the Paragon represented Intel’s foray into the MPP, or Massively Parallel Processing, market and would be based on their newly designed CPU, the i860. Interest ran high for MPP systems in the 1990s with many vendors besides Intel offering MPP products, including Ncube, Cray, Thinking Machines, and Maspar. To get the best possible performance from these new systems, researchers needed to come up with innovative techniques to take full advantage of what these new designs offered.
For one group of investigators working on a Paragon system at Sandia National Laboratories, their research resulted in winning the 1994 Gordon Bell Prize for the performance they attained using the boundary element method to solve systems of partial differential equations.
Even though Intel packaged Paragon systems with the OSF/1 operating system, another operating system, SUNMOS, gained its share of users. In a 1994 paper, Subhash Saini and Horst Simon compared application performance under both systems and found that each one demonstrated various advantages and disadvantages, that no one system was always better.
Robust processor performance depended on efficient data I/O performance and various parallel I/O schemes existed to make sure CPU’s in MPP systems were not starved for data. In his 1997 paper Caltech researcher Rajesh Bordawekar explored using a ‘collective I/O’ interface prototype on a Paragon system and found it improved overall performance as long as the inter-process communication (IPC) cost remained low.
In June 1994, a Paragon computer took the top position on the TOP500 list, this system being the 3,680 processor XPS/140 system at Sandia National Laboratories. As an indication of how fast the MPP market would advance, by November 1997 this system’s ranking had fallen to #18 with the new #1 held by an Intel-built computer named ASCI Red, also at Sandia, which was the first teraflop machine witha speed 10 times faster than a Paragon.
Given these marketplace dynamics, Intel announced in 1996 that it would discontinue manufacturing Paragon systems having sold about 100 machines. The Intel Paragon had performed well as a valuable testbed for parallel programming, operating system, and I/O development and earned many accolades along the way. Subsequent MPP systems benefited from this research, and they would go on to produce astonishingly high levels of performance.
